Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Generally, certain requirements are established for the flatness and thickness uniformity of the wafers. However, chucking of substrates with wafer shape (defined as the median surface of the wafer in its free state obtained from the front and back surfaces of the wafer) and thickness variations results in elastic deformation that can cause significant in-plane distortions (IPD). IPD may lead to errors in downstream applications such as overlay errors in lithographic patterning or the like. Therefore, providing the ability to predict/estimate IPD due to wafer shape in the chucking process and thus to control the wafer shape specification is a vital part of semiconductor manufacturing process.
The development and usage of a finite element (FE) model based IPD prediction is described in: Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners, Kevin Turner et al., Journal of Micro/Nanolithography, MEMS, and MOEMS, 8(4), 043015 (October-December 2009), which is herein incorporated by reference in its entirety. The FE model based IPD prediction utilizes full-scale 3-D wafer and chuck geometry information and simulates the non-linear contact mechanics of the wafer chucking mechanism, allowing the FE model to provide the most accurate prediction of IPD of the wafer surface. The FE model is developed and executed through a simulation-driven product development tool such as the ANSYS software package from ANSYS, Inc. However, FE model based IPD prediction is computationally expensive and may be complicated to setup, and therefore it is not suitable to be used in a high volume manufacturing environment.
Wafer higher order shape (HOS) information extracted from using wafer geometry tools, such as WaferSight from KLA-Tencor, can also be utilized to provide IPD prediction. For instance, wafer shape and HOS information may be used to simulate wafer chucking and predict its IPD. However, studies have shown that while HOS based IPD prediction may provide acceptable results for medium warp wafers, the accuracy of the IPD prediction degrades as the degree of wafer warp increases. The accuracy of HOS-based IPD prediction degrades primarily due to the fact that large 2nd order shape of the wafer (e.g., bowl, dome, saddle and the like) contributes to IPD during wafer chucking that is not completely represented by just the local higher order wafer slope. HOS, which is a local higher order slope based metric, is unable to capture well the IPD coma components (i.e., IPD distribution contours which closely resemble contours of coma components of Zernike polynomials) produced by large 2nd order shape and other lower order high magnitude shape components.
Therein lies a need for systems and methods for accurate and efficient prediction of in-plane distortions due to semiconductor wafer shape in the chucking process without the aforementioned shortcomings.